Speeduino
Loading...
Searching...
No Matches
board_teensy41.h
Go to the documentation of this file.
1#ifndef TEENSY41_H
2#define TEENSY41_H
3
4#if defined(CORE_TEENSY) && defined(__IMXRT1062__)
5
6/*
7***********************************************************************************************************
8* General
9*/
10 void initBoard();
11 uint16_t freeRam();
12 void doSystemReset();
13 void jumpToBootloader();
14 void setTriggerHysteresis();
15 void teensy41_customSerialBegin();
16 time_t getTeensy3Time();
17 #define PORT_TYPE uint32_t //Size of the port variables
18 #define PINMASK_TYPE uint32_t
19 #define COMPARE_TYPE uint16_t
20 #define COUNTER_TYPE uint16_t
21 #define SERIAL_BUFFER_SIZE 517 //Size of the serial buffer used by new comms protocol. For SD transfers this must be at least 512 + 1 (flag) + 4 (sector)
22 #define FPU_MAX_SIZE 32 //Size of the FPU buffer. 0 means no FPU.
23 #define BOARD_MAX_DIGITAL_PINS 54
24 #define BOARD_MAX_IO_PINS 54
25 #define BOARD_MAX_ADC_PINS 17 //Number of analog pins
26 #define EEPROM_LIB_H <EEPROM.h>
27 typedef int eeprom_address_t;
28 #define RTC_ENABLED
29 #define SD_LOGGING //SD logging enabled by default for Teensy 4.1 as it has the slot built in
30 #define RTC_LIB_H "TimeLib.h"
31 #define SD_CONFIG SdioConfig(FIFO_SDIO) //Set Teensy to use SDIO in FIFO mode. This is the fastest SD mode on Teensy as it offloads most of the writes
32
33 #define micros_safe() micros() //timer5 method is not used on anything but AVR, the micros_safe() macro is simply an alias for the normal micros()
34 //#define PWM_FAN_AVAILABLE
35 #define pinIsReserved(pin) ( ((pin) == 0) || ((pin) == 42) || ((pin) == 43) || ((pin) == 44) || ((pin) == 45) || ((pin) == 46) || ((pin) == 47) ) //Forbidden pins like USB
36
37
38/*
39***********************************************************************************************************
40* Schedules
41*/
42 /*
43 https://github.com/luni64/TeensyTimerTool/wiki/Supported-Timers#pit---periodic-timer
44 https://github.com/luni64/TeensyTimerTool/wiki/Configuration#clock-setting-for-the-gpt-and-pit-timers
45 The Quad timer (TMR) provides 4 timers each with 4 usable compare channels. The down compare and alternating compares are not usable
46 FUEL 1-4: TMR1
47 IGN 1-4 : TMR2
48 FUEL 5-8: TMR3
49 IGN 5-8 : TMR4
50 */
51 #define FUEL1_COUNTER TMR1_CNTR0
52 #define FUEL2_COUNTER TMR1_CNTR1
53 #define FUEL3_COUNTER TMR1_CNTR2
54 #define FUEL4_COUNTER TMR1_CNTR3
55 #define FUEL5_COUNTER TMR3_CNTR0
56 #define FUEL6_COUNTER TMR3_CNTR1
57 #define FUEL7_COUNTER TMR3_CNTR2
58 #define FUEL8_COUNTER TMR3_CNTR3
59
60 #define IGN1_COUNTER TMR2_CNTR0
61 #define IGN2_COUNTER TMR2_CNTR1
62 #define IGN3_COUNTER TMR2_CNTR2
63 #define IGN4_COUNTER TMR2_CNTR3
64 #define IGN5_COUNTER TMR4_CNTR0
65 #define IGN6_COUNTER TMR4_CNTR1
66 #define IGN7_COUNTER TMR4_CNTR2
67 #define IGN8_COUNTER TMR4_CNTR3
68
69 #define FUEL1_COMPARE TMR1_COMP10
70 #define FUEL2_COMPARE TMR1_COMP11
71 #define FUEL3_COMPARE TMR1_COMP12
72 #define FUEL4_COMPARE TMR1_COMP13
73 #define FUEL5_COMPARE TMR3_COMP10
74 #define FUEL6_COMPARE TMR3_COMP11
75 #define FUEL7_COMPARE TMR3_COMP12
76 #define FUEL8_COMPARE TMR3_COMP13
77
78 #define IGN1_COMPARE TMR2_COMP10
79 #define IGN2_COMPARE TMR2_COMP11
80 #define IGN3_COMPARE TMR2_COMP12
81 #define IGN4_COMPARE TMR2_COMP13
82 #define IGN5_COMPARE TMR4_COMP10
83 #define IGN6_COMPARE TMR4_COMP11
84 #define IGN7_COMPARE TMR4_COMP12
85 #define IGN8_COMPARE TMR4_COMP13
86
87 static inline void FUEL1_TIMER_ENABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN;} //Write 1 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
88 static inline void FUEL2_TIMER_ENABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
89 static inline void FUEL3_TIMER_ENABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
90 static inline void FUEL4_TIMER_ENABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
91 static inline void FUEL5_TIMER_ENABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
92 static inline void FUEL6_TIMER_ENABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
93 static inline void FUEL7_TIMER_ENABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
94 static inline void FUEL8_TIMER_ENABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
95
96 static inline void FUEL1_TIMER_DISABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;} //Write 0 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
97 static inline void FUEL2_TIMER_DISABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
98 static inline void FUEL3_TIMER_DISABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
99 static inline void FUEL4_TIMER_DISABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
100 static inline void FUEL5_TIMER_DISABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
101 static inline void FUEL6_TIMER_DISABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
102 static inline void FUEL7_TIMER_DISABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
103 static inline void FUEL8_TIMER_DISABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
104
105 static inline void IGN1_TIMER_ENABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
106 static inline void IGN2_TIMER_ENABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
107 static inline void IGN3_TIMER_ENABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
108 static inline void IGN4_TIMER_ENABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
109 static inline void IGN5_TIMER_ENABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
110 static inline void IGN6_TIMER_ENABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
111 static inline void IGN7_TIMER_ENABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
112 static inline void IGN8_TIMER_ENABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
113
114 static inline void IGN1_TIMER_DISABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
115 static inline void IGN2_TIMER_DISABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
116 static inline void IGN3_TIMER_DISABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
117 static inline void IGN4_TIMER_DISABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
118 static inline void IGN5_TIMER_DISABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
119 static inline void IGN6_TIMER_DISABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
120 static inline void IGN7_TIMER_DISABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
121 static inline void IGN8_TIMER_DISABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
122
123 //Bus Clock is 150Mhz @ 600 Mhz CPU. Need to handle this dynamically in the future for other frequencies
124 //#define TMR_PRESCALE 128
125 //#define MAX_TIMER_PERIOD ((65535 * 1000000ULL) / (F_BUS_ACTUAL / TMR_PRESCALE)) //55923 @ 600Mhz.
126 #define MAX_TIMER_PERIOD 55923UL
127 #define uS_TO_TIMER_COMPARE(uS) ((uS * 75UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
128 /*
129 To calculate the above uS_TO_TIMER_COMPARE
130 Choose number of bit of precision. Eg: 6
131 Divide 2^6 by the time per tick (0.853333) = 75
132 Multiply and bitshift back by the precision: (uS * 75) >> 6
133 */
134
135/*
136***********************************************************************************************************
137* Auxiliaries
138*/
139 #define ENABLE_BOOST_TIMER() PIT_TCTRL1 |= PIT_TCTRL_TEN
140 #define DISABLE_BOOST_TIMER() PIT_TCTRL1 &= ~PIT_TCTRL_TEN
141
142 #define ENABLE_VVT_TIMER() PIT_TCTRL2 |= PIT_TCTRL_TEN
143 #define DISABLE_VVT_TIMER() PIT_TCTRL2 &= ~PIT_TCTRL_TEN
144
145 //Ran out of timers, this most likely won't work. This should be possible to implement with the GPT timer.
146 #define ENABLE_FAN_TIMER() TMR3_CSCTRL1 |= TMR_CSCTRL_TCF2EN
147 #define DISABLE_FAN_TIMER() TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF2EN
148
149 #define BOOST_TIMER_COMPARE PIT_LDVAL1
150 #define BOOST_TIMER_COUNTER 0
151 #define VVT_TIMER_COMPARE PIT_LDVAL2
152 #define VVT_TIMER_COUNTER 0
153
154 //these probaply need to be PIT_LDVAL something???
155 #define FAN_TIMER_COMPARE TMR3_COMP22
156 #define FAN_TIMER_COUNTER TMR3_CNTR1
157
158/*
159***********************************************************************************************************
160* Idle
161*/
162 #define IDLE_COUNTER 0
163 #define IDLE_COMPARE PIT_LDVAL0
164
165 #define IDLE_TIMER_ENABLE() PIT_TCTRL0 |= PIT_TCTRL_TEN
166 #define IDLE_TIMER_DISABLE() PIT_TCTRL0 &= ~PIT_TCTRL_TEN
167
168/*
169***********************************************************************************************************
170* CAN / Second serial
171*/
172 #define USE_SERIAL3
173 #define secondarySerial_AVAILABLE
174 #define SECONDARY_SERIAL_T HardwareSerial
175
176 #include <FlexCAN_T4.h>
177 /*
178 //These are declared locally in comms_CAN now due to this issue: https://github.com/tonton81/FlexCAN_T4/issues/67
179 extern FlexCAN_T4<CAN1, RX_SIZE_256, TX_SIZE_16> Can0;
180 extern FlexCAN_T4<CAN2, RX_SIZE_256, TX_SIZE_16> Can1;
181 extern FlexCAN_T4<CAN3, RX_SIZE_256, TX_SIZE_16> Can2;
182 */
183 #define NATIVE_CAN_AVAILABLE //Disable for now as it causes lockup
184
185#endif //CORE_TEENSY
186#endif //TEENSY41_H
rshift
static uint32_t rshift(uint32_t a)
Bitwise right shift - generic, unoptimized, case.
Definition bit_shifts.h:349
Generated by doxygen 1.9.8