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board_teensy41.h
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1#ifndef TEENSY41_H
2#define TEENSY41_H
3
4#if defined(CORE_TEENSY) && defined(__IMXRT1062__)
5
6/*
7***********************************************************************************************************
8* General
9*/
10 void initBoard();
11 uint16_t freeRam();
12 void doSystemReset();
13 void jumpToBootloader();
14 void setTeensy41PinsHysteresis();
15 void teensy41_customSerialBegin();
16 bool pinIsSerial(uint8_t);
17 time_t getTeensy3Time();
18 uint8_t getSystemTemp();
19 #define COMPARE_TYPE uint16_t
20 #define SERIAL_BUFFER_SIZE 517 //Size of the serial buffer used by new comms protocol. For SD transfers this must be at least 512 + 1 (flag) + 4 (sector)
21 #define FPU_MAX_SIZE 32 //Size of the FPU buffer. 0 means no FPU.
22 #define BOARD_MAX_DIGITAL_PINS 54
23 #define BOARD_MAX_IO_PINS 54
24 #define BOARD_MAX_ADC_PINS 17 //Number of analog pins
25 #define EEPROM_LIB_H <EEPROM.h>
26 typedef int eeprom_address_t;
27 #define RTC_ENABLED
28 #define SD_LOGGING //SD logging enabled by default for Teensy 4.1 as it has the slot built in
29 #define RTC_LIB_H "TimeLib.h"
30 #define SD_CONFIG SdioConfig(FIFO_SDIO) //Set Teensy to use SDIO in FIFO mode. This is the fastest SD mode on Teensy as it offloads most of the writes
31
32 //#define PWM_FAN_AVAILABLE
33 #define pinIsReserved(pin) ( ((pin) == 0) || ((pin) == 42) || ((pin) == 43) || ((pin) == 44) || ((pin) == 45) || ((pin) == 46) || ((pin) == 47) || pinIsSerial((pin)) ) //Forbidden pins like USB
34
35
36/*
37***********************************************************************************************************
38* Schedules
39*/
40 /*
41 https://github.com/luni64/TeensyTimerTool/wiki/Supported-Timers#pit---periodic-timer
42 https://github.com/luni64/TeensyTimerTool/wiki/Configuration#clock-setting-for-the-gpt-and-pit-timers
43 The Quad timer (TMR) provides 4 timers each with 4 usable compare channels. The down compare and alternating compares are not usable
44 FUEL 1-4: TMR1
45 IGN 1-4 : TMR2
46 FUEL 5-8: TMR3
47 IGN 5-8 : TMR4
48 */
49 #define FUEL1_COUNTER TMR1_CNTR0
50 #define FUEL2_COUNTER TMR1_CNTR1
51 #define FUEL3_COUNTER TMR1_CNTR2
52 #define FUEL4_COUNTER TMR1_CNTR3
53 #define FUEL5_COUNTER TMR3_CNTR0
54 #define FUEL6_COUNTER TMR3_CNTR1
55 #define FUEL7_COUNTER TMR3_CNTR2
56 #define FUEL8_COUNTER TMR3_CNTR3
57
58 #define IGN1_COUNTER TMR2_CNTR0
59 #define IGN2_COUNTER TMR2_CNTR1
60 #define IGN3_COUNTER TMR2_CNTR2
61 #define IGN4_COUNTER TMR2_CNTR3
62 #define IGN5_COUNTER TMR4_CNTR0
63 #define IGN6_COUNTER TMR4_CNTR1
64 #define IGN7_COUNTER TMR4_CNTR2
65 #define IGN8_COUNTER TMR4_CNTR3
66
67 #define FUEL1_COMPARE TMR1_COMP10
68 #define FUEL2_COMPARE TMR1_COMP11
69 #define FUEL3_COMPARE TMR1_COMP12
70 #define FUEL4_COMPARE TMR1_COMP13
71 #define FUEL5_COMPARE TMR3_COMP10
72 #define FUEL6_COMPARE TMR3_COMP11
73 #define FUEL7_COMPARE TMR3_COMP12
74 #define FUEL8_COMPARE TMR3_COMP13
75
76 #define IGN1_COMPARE TMR2_COMP10
77 #define IGN2_COMPARE TMR2_COMP11
78 #define IGN3_COMPARE TMR2_COMP12
79 #define IGN4_COMPARE TMR2_COMP13
80 #define IGN5_COMPARE TMR4_COMP10
81 #define IGN6_COMPARE TMR4_COMP11
82 #define IGN7_COMPARE TMR4_COMP12
83 #define IGN8_COMPARE TMR4_COMP13
84
85 static inline void FUEL1_TIMER_ENABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL0 |= TMR_CSCTRL_TCF1EN;} //Write 1 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
86 static inline void FUEL2_TIMER_ENABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
87 static inline void FUEL3_TIMER_ENABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
88 static inline void FUEL4_TIMER_ENABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR1_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
89 static inline void FUEL5_TIMER_ENABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
90 static inline void FUEL6_TIMER_ENABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
91 static inline void FUEL7_TIMER_ENABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
92 static inline void FUEL8_TIMER_ENABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR3_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
93
94 static inline void FUEL1_TIMER_DISABLE(void) {TMR1_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;} //Write 0 to the TCFIEN (Channel Interrupt Enable) bit of channel 0 Status/Control
95 static inline void FUEL2_TIMER_DISABLE(void) {TMR1_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
96 static inline void FUEL3_TIMER_DISABLE(void) {TMR1_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
97 static inline void FUEL4_TIMER_DISABLE(void) {TMR1_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
98 static inline void FUEL5_TIMER_DISABLE(void) {TMR3_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
99 static inline void FUEL6_TIMER_DISABLE(void) {TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
100 static inline void FUEL7_TIMER_DISABLE(void) {TMR3_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
101 static inline void FUEL8_TIMER_DISABLE(void) {TMR3_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
102
103 static inline void IGN1_TIMER_ENABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
104 static inline void IGN2_TIMER_ENABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
105 static inline void IGN3_TIMER_ENABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
106 static inline void IGN4_TIMER_ENABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR2_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
107 static inline void IGN5_TIMER_ENABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL0 |= TMR_CSCTRL_TCF1EN;}
108 static inline void IGN6_TIMER_ENABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL1 |= TMR_CSCTRL_TCF1EN;}
109 static inline void IGN7_TIMER_ENABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL2 |= TMR_CSCTRL_TCF1EN;}
110 static inline void IGN8_TIMER_ENABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1; TMR4_CSCTRL3 |= TMR_CSCTRL_TCF1EN;}
111
112 static inline void IGN1_TIMER_DISABLE(void) {TMR2_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
113 static inline void IGN2_TIMER_DISABLE(void) {TMR2_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
114 static inline void IGN3_TIMER_DISABLE(void) {TMR2_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
115 static inline void IGN4_TIMER_DISABLE(void) {TMR2_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
116 static inline void IGN5_TIMER_DISABLE(void) {TMR4_CSCTRL0 &= ~TMR_CSCTRL_TCF1EN;}
117 static inline void IGN6_TIMER_DISABLE(void) {TMR4_CSCTRL1 &= ~TMR_CSCTRL_TCF1EN;}
118 static inline void IGN7_TIMER_DISABLE(void) {TMR4_CSCTRL2 &= ~TMR_CSCTRL_TCF1EN;}
119 static inline void IGN8_TIMER_DISABLE(void) {TMR4_CSCTRL3 &= ~TMR_CSCTRL_TCF1EN;}
120
121 // Need to handle this dynamically in the future for other frequencies
122 //#define TMR_PRESCALE 128
123 //#define MAX_TIMER_PERIOD ((65535U * 1000000ULL) / (F_BUS_ACTUAL / TMR_PRESCALE)) //55923 @ 600Mhz.
124 #if F_CPU == 600000000
125 //Bus Clock is 150Mhz @ 600 Mhz CPU.
126 #define MAX_TIMER_PERIOD 55923UL //Time per tick = 0.8533333
127 #define uS_TO_TIMER_COMPARE(uS) ((uS * 75UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
128 #elif F_CPU == 528000000
129 //Bus Clock is 132Mhz @ 528 Mhz CPU.
130 #define MAX_TIMER_PERIOD 63549UL //Time per tick = 0.96969696
131 #define uS_TO_TIMER_COMPARE(uS) ((uS * 66UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
132 #elif F_CPU == 450000000
133 //Bus Clock is 150Mhz @ 450 Mhz CPU.
134 #define MAX_TIMER_PERIOD 55923UL //Time per tick = 0.8533333
135 #define uS_TO_TIMER_COMPARE(uS) ((uS * 75UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
136 #elif F_CPU == 396000000
137 //Bus Clock is 132Mhz @ 396 Mhz CPU.
138 #define MAX_TIMER_PERIOD 63549UL //Time per tick = 0.96969696
139 #define uS_TO_TIMER_COMPARE(uS) ((uS * 66UL) >> 6) //Converts a given number of uS into the required number of timer ticks until that time has passed.
140 #elif F_CPU == 150000000
141 //Bus Clock is 75Mhz @ 150 Mhz CPU.
142 #define MAX_TIMER_PERIOD 111846UL //Time per tick = 1.706666
143 #define uS_TO_TIMER_COMPARE(uS) ((uS * 75UL) >> 7) //Converts a given number of uS into the required number of timer ticks until that time has passed.
144 #else
145 #error Unsupported CPU frequency.
146 #endif
147 /*
148 To calculate the above uS_TO_TIMER_COMPARE
149 Choose number of bit of precision. Eg: 6
150 Divide 2^6 by the time per tick (0.853333) = 75
151 Multiply and bitshift back by the precision: (uS * 75) >> 6
152 */
153
154
155/*
156***********************************************************************************************************
157* Auxiliaries
158*/
159 #define ENABLE_BOOST_TIMER() PIT_TCTRL1 |= PIT_TCTRL_TEN
160 #define DISABLE_BOOST_TIMER() PIT_TCTRL1 &= ~PIT_TCTRL_TEN
161
162 #define ENABLE_VVT_TIMER() PIT_TCTRL2 |= PIT_TCTRL_TEN
163 #define DISABLE_VVT_TIMER() PIT_TCTRL2 &= ~PIT_TCTRL_TEN
164
165 //Ran out of timers, this most likely won't work. This should be possible to implement with the GPT timer.
166 #define ENABLE_FAN_TIMER() TMR3_CSCTRL1 |= TMR_CSCTRL_TCF2EN
167 #define DISABLE_FAN_TIMER() TMR3_CSCTRL1 &= ~TMR_CSCTRL_TCF2EN
168
169 #define BOOST_TIMER_COMPARE PIT_LDVAL1
170 #define BOOST_TIMER_COUNTER 0
171 #define VVT_TIMER_COMPARE PIT_LDVAL2
172 #define VVT_TIMER_COUNTER 0
173
174 //these probaply need to be PIT_LDVAL something???
175 #define FAN_TIMER_COMPARE TMR3_COMP22
176 #define FAN_TIMER_COUNTER TMR3_CNTR1
177
178/*
179***********************************************************************************************************
180* Idle
181*/
182 #define IDLE_COUNTER 0
183 #define IDLE_COMPARE PIT_LDVAL0
184
185 #define IDLE_TIMER_ENABLE() PIT_TCTRL0 |= PIT_TCTRL_TEN
186 #define IDLE_TIMER_DISABLE() PIT_TCTRL0 &= ~PIT_TCTRL_TEN
187
188/*
189***********************************************************************************************************
190* CAN / Second serial
191*/
192 #define SECONDARY_SERIAL_T HardwareSerial
193
194 #include <FlexCAN_T4.h>
195 /*
196 //These are declared locally in comms_CAN now due to this issue: https://github.com/tonton81/FlexCAN_T4/issues/67
197 extern FlexCAN_T4<CAN1, RX_SIZE_256, TX_SIZE_16> Can0;
198 extern FlexCAN_T4<CAN2, RX_SIZE_256, TX_SIZE_16> Can1;
199 extern FlexCAN_T4<CAN3, RX_SIZE_256, TX_SIZE_16> Can2;
200 */
201 #define NATIVE_CAN_AVAILABLE //Disable for now as it causes lockup
202
203#endif //CORE_TEENSY
204#endif //TEENSY41_H
rshift
static uint32_t rshift(uint32_t a)
Bitwise right shift - generic, unoptimized, case.
Definition bit_shifts.h:348
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